In the fabrication of a printed circuit board (PCB) it is desirable to provide electrical connection of circuits at various layers within the PCB. This is typically done using a plated through hole (PTH). A PTH is typically formed using the steps of drilling, desmearing, and plating. The hole quality before plating has an impact on the robustness of the finished PTH, e.g., its ability to withstand thermal cycling, such as through multiple high temperature solder reflows, without fatiguing to the point of failure. Standard practice is to judge the hole quality by visually observing the roughness of the hole sidewall.
There are several variables in the drilling process which can affect the hole roughness. The drill bit design, the drill bit sharpness, the dielectric material being drilled, the rotation of the drill bit (speed) and the rate at which the drill bit is forced down through the PCB (feed) all can play a role in the hole roughness.
Typically, a desmear process is used after drilling to remove dielectric material which may be smeared onto the inner plane edges exposed during drilling, due to the nature of the dielectric and the localized heat generated by the drilling process. While other techniques, such as plasma, can be used, a typical desmear process consists of swelling the resin with an organic solvent, etching the resin with a hot alkaline potassium permanganate solution, and neutralizing the alkaline permanganate with an acid such as sulfuric acid. Various parameters such as the time and temperature in the sweller, and time, temperature in the permanganate etch, as well as the permanganate concentration, can affect the dielectric etching. If the etching is not aggressive enough, smear will remain on the plane edges exposed by drilling and can result in a poor electrical/mechanical connection when the PTH is plated. If the etch is too aggressive, the resin can be etched back too much resulting in excessive hole roughness that can cause defects.
Following desmear, the PTH is plated, typically with copper. A variety of plating processes can be used, such as full panel plate or pattern plate. A typical plating process involves applying a seed layer in the hole, such as colloidal palladium. An electroless copper bath is used to deposit a layer of copper thick enough to carry some current, then the PCB is plated in an electrolytic copper bath. Since the plating follows the topography of the PTH sidewall, the roughness of the copper plating is influenced by the roughness of the sidewall prior to plating.
The PTH reliability is strongly influenced by the sidewall roughness, and that the sidewall roughness is influenced by the drilling process and the desmear process, and that the drill, desmear, and plate operations need to be co-optimized to achieve the best results. Standard practice is to experimentally vary the drill, desmear, and plate parameters when a new process is needed, such as for a new dielectric material or a new PCB thickness. The effectiveness of a given set of parameters is typically determined by visually observing the sidewall roughness from a cross section of a PTH. The final set of parameters is typically determined by reliability testing, such as Current Induced Thermal Cycling (CITC), Interconnect Stress Testing (IST), or thermal cycling.
IST and CITC utilize testing of current flow/resistance through a part of a circuit board. If the resistance of a circuit (containing plated through holes) changes during testing to a level of about a 10% increase in resistance, a structural failure has occurred within the interconnect. These methods determine a change in resistance of plated barrels, a commonly used term referring to a plurality of plated-through holes, and/or internal connections as they undergo thermal cycling.
IST involves passing a predetermined constant direct current (DC) through a coupon. The DC increases the temperature of the metals of the coupon by resistive heating and adjacent materials of the coupon by conduction. The increased temperature of the coupon is directly proportional to the measured resistance and the amount of current that is passed through the conductors, pads and holes.
An IST system can raise the temperature of the coupon through resistive heating to between about 130° C. and about 300° C., such as about 150° C. and about 260° C., for example about 230° C. Once the temperature has been increased to a particular temperature, the increased temperature may be maintained for between about 10 seconds and about 10 minutes, such as about 1 minute and about 5 minutes, such as about 2 minutes and about 3 minutes. The system then discontinues electric current and allows/initiates cooling. Cooling may be performed by forced air cooling, allowing the coupon to return to ambient. One heating and cooling constitutes a single thermal cycle. IST processes of the present disclosure may be performed on any suitable IST processing equipment, an example of which may be obtained from PWB Interconnect Solutions, Inc. (Canada).
During each thermal cycle, the IST system may continuously monitor the resistance changes of the coupon. As the temperature of an interconnect increases (or decreases), the resistance values of the interconnect (i.e. traces, pads and hole barrels) may also measure proportional changes. The IST method is designed to quantify an ability of the interconnect structures (the coupon) to withstand the thermal/mechanical stresses. Testing may be completed on the as manufactured and the assembled state, which assists an assessment of when the product reaches the point of interconnect degradation/failure.
If interconnects have few defects, for example, if the quality of the interconnects is unaffected for several hundreds of these cycles, the resistance values before, during and after the cycles are substantially similar, if not the same. If the measured resistance changes from one cycle to a subsequent cycle, whether positive or negative, then one or more defects within the interconnect may have formed. When a failure state has initiated in the coupon, the measured difference in resistance is usually very small (sub-milliohm). When larger resistance changes are detected, a defect that ultimately leads to a product failure has initiated/started. IST provides determination of when defect(s) begins to develop or have already developed, as well as how rapidly defect(s) accumulate. Changes in current may be monitored on three circuits: the first may be the heating circuit which carries the current through the internal layers, and can monitor the resistance changes, measuring for interconnect separations or foil cracking. The second and third circuits receive no current—these circuits are responsible for measuring the PTH, blind, buried or micro-via interconnect reliability. The system may repeat the cycles, measuring the resistance continuously until a rejection criteria is achieved; rejection could be set at a predetermined increase in resistance or a pre-set number of cycles. Data collection, reporting and analysis may be performed by any suitable software. The system may graphically display the performance of each coupon for a particular test and provides feedback regarding defect initiation and ultimate interconnect failure. The IST system allows determination of interconnect failure before a larger overall failure occurs.
IST utilizes the internal interconnect to heat the coupon; heat generation is created throughout the daisy chain of copper conductors, pads and vias. Throughout testing, any local areas of increased resistance within an interconnect will cause localized heating to occur. Measurements above a 1% increase in elevated resistance signify failure initiation. The increased resistance is caused by areas of localized strain.
Software may calculate and display the resistance of a test temperature, e.g., between about 30° C. and about 350° C., such as about 50° C. and about 270° C. An equation used to calculate a desired resistance is as follows: Target Resistance=Rrm×(1+αT[Th−Trm]), where αT is the estimated thermal coefficient of resistance for the interconnect, Rrm is the resistance of a coupon at ambient temperature, Th is test temperature, and Trm is ambient/room temperature (approximately 25° C.). System software calculates and displays the resistance change, which is adjustable from a 1% to a 100% increase. A typical failure threshold value is a 10% change in resistance. An equation to calculate the failure threshold is as follows: Failure Threshold=(RT1×Rr)+RT1. Failure Threshold is in resistance. RT1 is resistance of coupon at test temperature for Cycle 1 and Rr is resistance change (typically 10%).
A coupon's resistance “delta” (the difference of resistance of a coupon at test temperature for Cycle 2) increases (positively) as failure initiates and progresses. The rate of change in delta indicates defect formation (failure) within the barrel and/or internal connections. When a coupon delta reaches an undesired resistance, the cycle testing is stopped for that coupon, providing failure analysis of a coupon before the extent of damage affects the ability of the coupon to be analyzed.
As with IST, Current Induced Thermal Cycling (CITC) determines a failure based on a percentage change in the bulk resistance of the coupon at the designated temperature. When percentage change increases to an undesired level, a test is terminated for a coupon. A test coupon may be resistance heated by passing direct current through the coupon to bring the temperature of the copper to a desired temperature. Like IST, CITC involves one or more cycles of temperature increase and subsequent cooling. CITC processes of the present disclosure may be performed on any suitable CITC processing equipment, which may be obtained from i3 Electronics (USA).
In some embodiments, a CITC process includes a coupon with an electrical net. The net includes via structure connected by circuit lines in a daisy chain. Direct current may be passed through the electrical net to provide heat to the coupon until a desired increased temperature is achieved, followed by removing the direct current and cooling the coupons to about ambient temperature. This sequence represents one cycle of CITC. Cycling may be repeated for a desired number of cycles and/or until a failure is detected by measuring a temperature coefficient of resistance (TCR).
For CITC, the TCR of each coupon may be determined for typically from about 2 to about 4 coupons. IST temperature test ranges may be between about 15° C. and about 300° C., such as about 23° C. and about 220° C. Like IST, CITC is a thermally cyclic process. The number of cycles for CITC may be between about 2 cycles and about 50 cycles, such as about 5 cycles and about 15 cycles, for example about 10 cycles. A temperature ramp rate of a coupon for CITC may be between about 1° C./second and about 20° C./second, such as about 2° C./second and about 7° C./second, for example 3° C. A dwell time at an elevated test temperature may be between about 5 seconds and about 5 minutes, such as about 20 seconds, and about 60 seconds, for example 40 seconds.
At each temperature during a CITC test, a computer may control an oven temperature and monitor and record an equilibrium resistance. TCR may be calculated for each coupon as follows: TCR(T)=[(Rh−Rrm)]/[(Th−Trm)×Rrm. TCR(T) is the calculated TCR for a coupon as a function of test temperature (T), Th is the temperature of a coupon at oven temperature, Rh is the resistance of a coupon at an oven temperature, Rrm is a resistance of a coupon at ambient temperature, and Trm is an ambient temperature (for example, about 23° C.).
A computer may calculate and display a coupon test temperature using the following equation: T=Trm+[(R−Rrm)/(Rrm×TCR(T))]. TCR(T) is the measured thermal coefficient of resistance for the coupon(s), Rrm is the resistance of a coupon at ambient temperature measured at the start of each cycle, T is a coupon test temperature calculated at 1 second interval, R is a coupon resistance measured at 1 second intervals, and Trm is the ambient temperature measured at each cycle (for example, about 23° C.). Alternatively, this equation may be expressed in terms of the target resistance that is equivalent to the targeted increased temperature for the coupon and cycle, as follows: Target Resistance=Rrm×(1+TCR(Th)[Th−Trm]). Th is the target high test temperature. If defects become too prevalent, a failure will begin to occur, for example, when R exceeds between about 1% and about 10%, and/or final Rrm(n) after cooling a coupon is between about 3% and about 10% difference from Rrm(0) at the start of the CITC test before the first cycle.
A CITC process may include placing coupon(s) in a table top test fixture that includes one or more cooling fans and quick connect housings. Direct current may be used to heat the one or more coupon(s) at a predetermined ramp rate up to a test temperature. When a test temperature is achieved, the temperature is maintained for a dwell time, followed by cooling the coupon(s) with the one or more cooling fans. The coupon(s) undergo thermal cycles until one of the rejection criteria described above occurs or a maximum desired number of cycles is achieved.
A computer may monitor and record changes in resistance of the plated barrel throughout the CITC process.
Such methods are designed to monitor these changes and stop the stressing at a pre-determined (low) level of failure. However, these methods typically involve thermal cycling which is time-consuming, expensive, and only 4 coupons can be tested at one time, necessitating multiple runs to complete a study of a circuit board. More importantly, these methods are limited in that defects in the plated through holes are detected close to or after a failure (open circuit) state.
Therefore, there is a need in the art for quantitative and precise defect detection methods for plated through holes, which may be used complimentarily to CITC and IST or as a diagnostic to determine whether CITC or IST should be performed at all.